1. Technical Field
Embodiments of the present disclosure may generally relate to a semiconductor device and a semiconductor system and, more particularly, to adjusting the levels of a plurality of internal voltages of the semiconductor device and/or semiconductor system.
2. Related Art
A semiconductor memory device may receive a power supply voltage VDD and a ground voltage VSS from an exterior. The semiconductor memory device may generate and use internal voltages required for internal operations thereof. The voltages required for the internal operations of the semiconductor memory device may include a core voltage VCORE, a high voltage VPP, and a back-bias voltage VBB. The core voltage VCORE may be supplied to a memory core area. The high voltage VPP may be used in the driving or over-driving of a word line. The back-bias voltage VBB may be supplied as a bulk voltage of a NMOS transistor of the core area.
Since the core voltage VCORE is supplied by reducing the power supply voltage VDD inputted from the exterior to a predetermined voltage, but the high voltage VPP has a voltage with a level higher than that of the power supply voltage VDD inputted from the exterior and the back-bias voltage VBB substantially maintains a voltage with a level lower than that of the ground voltage VSS inputted from the exterior, a charge pump circuit for supplying charge for the high voltage VPP and the back-bias voltage VBB is required in order to supply the high voltage VPP and the back-bias voltage VBB.